1. Field of the Invention
The present invention relates to a solid-state image pickup device applied to a digital still camera, a digital video camera and the like, and an image pickup device including the solid-state image pickup device.
Priority is claimed on Japanese Patent Application No. 2011-007777, filed Jan. 18, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
In recent years, since the performance of a MOS type solid-state image pickup element capable of integrating a peripheral circuit into a chip has significantly improved, the MOS type solid-state image pickup element has been widely proliferated, in place of a CCD type solid-state image pickup element. In the MOS type image pickup element, a plurality of pixels arranged in a two-dimensional manner are provided on the image capturing surface thereof, wherein each pixel converts incident light into signal charge to generate a pixel signal (an image signal). A driving method of the MOS type solid-state image pickup element includes a rolling shutter method in which an exposure start time and an exposure end time are different from in each pixel, and a global shutter method in which the exposure start time and the exposure end time are the same in all pixels.
A MOS type solid-state image pickup element employing the global shutter method includes a photoelectric conversion unit, such as a photodiode, configured to generate a signal charge corresponding to an exposure light amount, a charge holding unit (a charge accumulation unit) configured to temporarily accumulate the signal charge generated in the photoelectric conversion unit, a switching transistor configured to transmit or reset a signal charge, and the like.
FIG. 13 illustrates the configuration of a pixel 100 arranged in a two-dimensional manner on an image capturing surface of a MOS type solid-state image pickup element employing a global shutter method. A photodiode (PD) 101 is a photoelectric conversion element configured to convert incident light into a signal charge (photoelectric conversion) and accumulate the signal charge. A transmission transistor 102 is a transistor configured to transmit the signal charge generated in the photodiode 101 to a charge holding unit (FD) 103. The charge holding unit 103 is floating diffusion (FD) configured to hold the signal charge accumulated in the photodiode 101. An FD reset transistor 104 is a transistor configured to reset (initialize) the potential (that is, signal charge) of the charge holding unit 103.
An amplifying transistor 105 is a transistor configured to amplify and read the voltage level of the charge holding unit 103. A select transistor 106 is a transistor configured to select a pixel and transfer the output of the amplifying transistor 105 to a vertical signal line 114. A PD reset transistor 107 is a transistor configured to reset (initialize) the potential (that is, the signal charge) of the photodiode 101. Remaining elements, other than the photodiode 101, are shielded from light.
A power line 110 is configured to supply a power supply voltage VDD to each pixel, and is electrically connected to a drain terminal of the amplifying transistor 105, a drain terminal of the FD reset transistor 104, and a drain terminal of the PD reset transistor 107. An FD reset line 111 is a signal line configured to receive an FD reset pulse φRMi (i denotes a row number and has the same meaning in the following description) for resetting the charge holding units 103 in pixels of one row, and is electrically connected to gate terminals of the FD reset transistors 104 in the pixels of one row. A transmission line 112 is a signal line configured to receive a row transmission pulse φTRi for transmitting the signal charge generated in the photodiodes 101 in the pixels of one row to the charge holding units 103 in the pixels, and is electrically connected to gate terminals of the transmission transistors 102 in the pixels of one row.
A PD reset line 115 is a signal line configured to receive a PD reset pulse φRPDi for resetting the photodiodes 101 in the pixels of one row, and is electrically connected to gate terminals of the PD reset transistors 107 in the pixels of one row. A selection line 113 is a signal line configured to receive a row selection pulse φSEi for selecting the pixels of one row, and is electrically connected to gate terminals of the select transistors 106 in the pixels of one row. As described above, with such a pixel configuration using the five transistors, a photoelectric conversion function, a reset function, an amplification read function, a temporary memory function, and a selection function are performed.
FIG. 14 illustrates a configuration in which the pixels illustrated in FIG. 13 are arranged on an image capturing surface of a solid-state image pickup element in 3 rows×3 columns. In FIG. 14, a pixel unit 200 has a configuration in which pixels 100 are two-dimensionally arranged in a 3×3 matrix form. Each pixel 100 has a configuration illustrated in FIG. 13.
A vertical scanning circuit 300 controls the driving of the pixel unit 200 in units of rows. In order to perform this driving control, the vertical scanning circuit 300 includes unit circuits 301-1, 301-2, and 301-3, wherein the number of the unit circuits is the same as the number of rows. Furthermore, each unit circuit includes control units 302-i, 303-i, 304-i, and 305-i (i=1, 2, 3).
The control unit 302-i controls the FD reset pulse φRMi (i=1, 2, 3), which resets the charge holding units 103 in pixels of one row, through the FD reset line 111 independently in each row. The control unit 303-i controls the row transmission pulse φTRi (i=1, 2, 3), which transmits a signal charge of the pixels 100 of one row to the charge holding units 103 of the pixels 100, through the transmission line 112 independently in each row. The control unit 304-i controls the PD reset pulse φRPDi (i=1, 2, 3), which resets the photodiodes 101 of the pixels 100 of one row, through the PD reset line 115 independently in each row. The control unit 305-i controls the row selection pulse φSEi (i=1, 2, 3), which selects the pixels 100 of one row from which signals are read, through the selection line 113 independently in each row. Signals of the pixels 100 of a row selected by the row selection pulse φSEi are output to vertical signal lines 114 provided corresponding to columns.
Power lines 150 are provided corresponding to the columns and connected to the vertical signal lines 114, thereby forming source follower circuits together with the amplifying transistors 105 in the pixels 100. Column processing circuits 350 are provided corresponding to the columns and perform a clamp operation or an amplification operation with respect to pixel signals output to the vertical signal lines 114. A horizontal reading circuit 400 selects a pixel column from which pixel signals are read, and outputs the pixel signals from the pixel column through an output terminal 410. An analog-to-digital (AD) converter 500 performs AD conversion with respect to the pixel signals output from the output terminal 410. A frame memory 600 holds the pixel signals having passed through the AD conversion. A difference circuit 700 performs a difference process (a subtraction process) with respect to the pixel signals output from the AD converter 500 and the pixel signals held by the frame memory 600. In addition the power line 110 configured to supply the power supply voltage VDD is not illustrated in FIG. 14.
The following description will be given based on an operation for reading pixel signals using the global shutter method when the MOS type solid-state image pickup element illustrated in FIG. 14 is applied to the image capturing of a still image by a digital camera and the like. FIG. 15 illustrates an operation performed using the global shutter method. For the purpose of convenience, a description will be given using a solid-state image pickup element in which pixels are two-dimensionally arranged in a 3×3 matrix form, similarly to FIG. 14.
If a photographing start signal is input, the PD reset pulses φRPDi of all rows are changed from an “L” level to an “H” level and thus the PD reset transistors 107 of all pixels 100 are turned on, so that the photodiodes 101 of all pixels 100 are reset. Next, the FD reset pulse φRMi of a first row is changed from an “L” level to an “H” level and thus the FD reset transistor 104 of the first row is turned on, so that the charge holding unit 103 of the first row is reset.
Next, after the FD reset pulse φRMi of the first row is changed from an “H” level to an “L” level and thus the FD reset transistor 104 is turned off, the row selection pulse φSEi of the first row is changed from an “L” level to an “H” level and thus the select transistor 106 of the first row is turned on, so that a voltage (a reset level) of the charge holding unit 103 of the first row is output to the horizontal reading circuit 400 through the column processing circuit 350 as a reset signal. The horizontal reading circuit 400 sequentially outputs reset signals through the output terminal 410 in the horizontal direction.
The output reset signal of the pixel 100 of the first row is A/D converted by the AD converter 500, and is output to and held in the frame memory 600. Even after a second row, reset signals are read, and reset signals of all pixels 100 are held in the frame memory 600, similarly to the first row.
Next, the PD reset pulses φRPDi of all rows are changed from an “H” level to an “L” level and thus the PD reset transistors 107 of all pixels 100 are turned off, so that the photodiodes 101 of all pixels 100 start to accumulate signal charge. Accordingly, exposure (signal accumulation) of all pixels 100 is started. If a desired accumulation time elapses, the row transmission pulses φTRi of all rows are changed from an “L” level to an “H” level and thus the transmission transistors 102 of all pixels 100 are turned on, so that a signal charge accumulated in the photodiodes 101 of all pixels 100 is transmitted to the charge holding units 103. That is, the exposure (signal accumulation) is completed. The period from the charge accumulation start to the charge accumulation end corresponds to an exposure period (an accumulation period).
Immediately after the transmission operation of the signal charge is completed, the PD reset pulses φRPDi of all rows are changed from an “L” level to an “H” level and thus the PD reset transistors 107 of all pixels 100 are turned on, so that the photodiodes 101 of all pixels 100 enter a reset state. Next, the row selection pulse φSEi of the first row is changed from an “L” level to an “H” level and thus the select transistor 106 of the first row is turned on, so that a voltage (an optical signal level) of the charge holding unit 103 of the first row is output to the horizontal reading circuit 400 through the column processing circuit 350 as an optical signal. The horizontal reading circuit 400 sequentially outputs optical signals through the output terminal 410 in the horizontal direction.
The output optical signal of the pixel 100 of the first row is A/D converted by the AD converter 500, and is output to the difference circuit 700. The difference circuit 700 obtains a difference between the optical signal of the pixel 100 of the first row and the reset signal of the pixel 100 of the first row held in the frame memory 600, extracts only an optical signal component, and outputs the optical signal component to a circuit of a subsequent stage as an image capturing signal. In this operation, it is possible to remove reset noise of the charge holding unit 103, resulting in the achievement of a signal with a high S/N.
Next, even after the second row, an operation similar to the first row is performed, so that pixel signals of all pixels 100 are read. These signals are processed in an image processing circuit of a subsequent stage (not illustrated), resulting in the generation of a still image. Through the above-mentioned operation, it is possible to perform a global shutter operation for simultaneously performing exposure and charge accumulation in all pixels. Technology related to the MOS type solid-state image pickup element has been disclosed in Japanese Unexamined Patent Application, First Publication No. 11-261896.
A general digital camera is powered on, regularly performs image capturing in units of frames to generate a moving image signal, and displays a live view image (a moving image) on a display unit based on the generated moving image signal. During the display of the live view image, if a user gives a photographing instruction which is an acquirement instruction of a still image, the digital camera stops generating the moving image signal, performs photographing to generate a still image signal, and records the generated still image signal on a recording medium. At the time of the generation of the still image signal, for example, the global shutter operation is performed.
However, since it is not possible to update the live view image at the time of photographing of the still image, a phenomenon in which the same image is displayed on the display unit in the period for which update is not possible, or no image is displayed due to a blackout of the display unit may occur. Furthermore, in the above-mentioned global shutter operation, since it is necessary to perform both a read operation for a reset signal before exposure and a read operation for an optical signal after the exposure, a sequence period necessary for photographing one still image is increased due to an increase in the number of pixels.
In order to solve these problems, Japanese Unexamined Patent Application, First Publication No. 2010-183795 (for example, FIG. 18 to FIG. 21) discloses a method in which pixels of a solid-state image pickup element are divided into a plurality of pixel groups, two output systems for a still image and a moving image (live view) are provided, and a pixel group not used for reading a still image signal is used for reading a moving image signal, so that the reading of the still image signal and the reading of the moving image signal are simultaneously performed.
In the related art, in the case of performing the live view (the moving image) display during the photographing of the still image, the still image signal and the moving image signal are simultaneously read, so that it is possible to reduce a period for which the live view image may not be updated. However, of the two output systems, since one is fixed for reading the still image signal, the other is fixed for reading the moving image signal, and since the reading of the still image signal having a large number of pixels is used only for one output system, there is a limitation in reducing a still image photographing time.